Presentation
Svacoder: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis
DescriptionSystemVerilog Assertions (SVAs) are crucial for hardware verification. Recent studies leverage LLMs to translate natural language properties to SVAs (NL2SVA), but they perform poorly due to limited data. We propose a data synthesis framework to tackle two challenges: the scarcity of real-world SVA corpora and the lack of methods to promote the NL-SVA semantic equivalence. For the former, large-scale RTL code is used to guide LLMs to generate real-world SVAs; for the latter, bidirectional NL-SVA translation maintains semantic consistency. With
the synthesized data, we train SVACoder, a series of SVA generation models. Notably, SVACoder-14B achieves 75.8% on NL2SVA-Human and 84.0% on NL2SVA-Machine in Func.@1, matching or exceeding advanced LLMs like GPT-5 and DeepSeek-R1.
the synthesized data, we train SVACoder, a series of SVA generation models. Notably, SVACoder-14B achieves 75.8% on NL2SVA-Human and 84.0% on NL2SVA-Machine in Func.@1, matching or exceeding advanced LLMs like GPT-5 and DeepSeek-R1.
Event Type
Research Manuscript
TimeMonday, July 273:54pm - 4:06pm PDT
LocationMtg Room 101A