Presentation
METRIC: An MDS-Analog ECC with Minimum Two-Column Redundancy for Fault-Tolerant, Layer-Aware IMC Architecture
DescriptionNeural networks from CNNs to LLMs achieve remarkable success, yet analog computing-in-memory (CIM) using memristor crossbars suffers from computational inaccuracies caused by device defects and circuit noise. While tolerating small errors, significant outliers must be corrected. We propose MECA-CIM, a Maximum Distance Separable (MDS) error correction framework requiring only two redundancy columns. Leveraging Hessian trace-based sensitivity quantification, we introduce layer-wise adaptive protection allocation. Our analog-domain syndrome decoder enables efficient error detection and correction with minimal latency. Experimental results demonstrate robust outlier resistance across CNNs and Transformers, achieving large area-energy-delay product (AEDP) reduction compared to conventional ECC systems.
Event Type
Research Manuscript
TimeMonday, July 2710:30am - 10:43am PDT
LocationMtg Room 202C
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