Presentation
Chipmodeler: LLM-Aided Reference Model Design for Agile Hardware Verification
DescriptionAs integrated circuit designs grow in complexity, reference model development for functional verification faces increasing challenges. We propose ChipModeler, an LLM-assisted platform that streamlines reference model generation and verification through design standardization and hierarchical agile modeling. By employing a building-block generation strategy, ChipModeler significantly enhances both efficiency and quality. Evaluation on 300 diverse designs shows up to 58.99% improvement in performance, a 9.18× increase in generation capacity, and a 7.11× acceleration in design and validation cycles compared to manual methods, demonstrating ChipModeler's effectiveness in automating reference model development.
Event Type
Research Manuscript
TimeMonday, July 275:18pm - 5:30pm PDT
LocationMtg Room 101A
Similar Presentations