Presentation
Design Technology Co-Optimization for Network on Chip in High Performance CPUs at 3nm Node Using Monolithic 3D and Backside Interconnect Technologies
DescriptionWith the rapidly growing demand of cloud computing and large-scale AI models, many-core systems are facing challenges of longer global interconnect distances in Network-on-Chip (NoC). Though conventional 2D NoCs can apply relative high metal layer for global routing, the extensive repeater insertion for long-distance transmission causes significant number of via-stacking, leading to performance degradation. Targeting high-performance CPU clusters at 3nm node, this work adopts a design–technology co-optimization (DTCO) framework to evaluate long-distance NoC interconnects across four implementation schemes: conventional frontside 2D (F2D), frontside 3D (F3D) with M3D integration, F2D with backside power delivery network (BSPDN), and backside 2D (B2D) leveraging wafer backside signal routing & PDN. Based on post-layout extraction of the ARM Neoverse CSS N2 computing tile, we incorporate realistic PDN characteristics, technology-dependent RC modeling, and IR-drop-aware circuit simulation. Results show that F3D and B2D reduce delay by 53% and 68%, and energy–delay product (EDP) by 32% and 63%, respectively, compared with F2D. F2D-BSPDN achieves performance comparable to F3D. System-level NoC evaluations further demonstrate that F3D/B2D enable 2.1×/3.1× feasible link frequencies of F2D, and lower average NoC latency of F2D by 23%/35%. The DTCO analysis indicates that while F2D remains adequate for small cores (Cortex-A76), B2D is the optimal choice for mid-core (Cortex-A720, X4) and large-core (Cortex-X925, CSS N2) clusters, with F3D providing secondary benefits through repeater relocation. These findings identify backside interconnect as
Event Type
Research Manuscript
TimeMonday, July 2711:50am - 12:03pm PDT
LocationMtg Room 202C
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