Presentation
WSC-Cost: An Accurate Cost Modeling Framework for Wafer-Scale Chips
DescriptionAs Moore's Law nears its physical limits, wafer-scale chips (WSCs) are emerging as a promising platform for LLM workloads, offering extreme performance, and favorable cost. However, prior work seldom quantifies WSC cost end-to-end, hindering principled design-space exploration. We introduce WSC-Cost, a unified WSC cost model with two orthogonal dimensions. Horizontally, WSC-Cost quantifies mask-stitching costs across multiple metal layers. Vertically, it accounts for interposer fabrication and assembly costs. We validate WSC-Cost using open-source cost data and an in-house WSC prototype. WSC-Cost enables the co-optimization of wafer-scale systems and further provides cost-driven insights to unleash the full potential of wafer-scale integration.
Event Type
Research Manuscript
TimeTuesday, July 282:34pm - 2:47pm PDT
LocationMtg Room 201B