Presentation
Flip-FET-Based VLSI Design Framework with Congestion-Aware Dual-Side Routing
DescriptionThis paper presents a comprehensive Flip-FET-based VLSI design framework that leverages both front-side and back-side metal layers for congestion-aware routing optimization. Starting from the placement result, we formulate an integer linear programming (ILP) model to determine standard cells' pin assignments that minimize dual-side nets and alleviate regional congestion simultaneously. Routing is then performed with optimal nTSV insertion for dual-side nets using an RSMT construction approach. Experimental results demonstrate that the proposed framework achieves 78.8% reduction in maximum congestion and 68.6% reduction in DRVs over a commercial design tool.
Event Type
Research Manuscript
TimeTuesday, July 285:18pm - 5:30pm PDT
LocationMtg Room 202AB
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