Presentation
Hyperwafer: Communication-Aware Sparse Matrix Multiplication on Wafer-Scale Chips
DescriptionSparse-matrix sparse-matrix multiplication (SpGEMM) is a key kernel across many domains, yet its performance on modern architectures is dominated by highly irregular data movement. Wafer-scale chips (WSCs) offer unprecedented bandwidth and massive parallelism, making them a compelling platform for SpGEMM. However, sparsity-induced irregularity generates substantial communication overheads, resulting in severe underutilization.
In this work, we present HyperWafer, the first communication-aware SpGEMM framework for WSCs, combining a hypergraph-guided execution model with dedicated architectural support. HyperWafer captures SpGEMM's inherently high-order dataflow dependencies, which arise from multiway row sharing and overlapping reduction scopes, using a weighted hypergraph abstraction that enables communication-centric partitioning and topology-aware mapping aligned with the wafer's physical bandwidth distribution. To efficiently realize this model, HyperWafer integrates a sparsity-aware SpGEMM execution engine that sustains high per-PE throughput under irregular workloads together with a lightweight, congestion-sensitive runtime routing substrate that preserves effective on-wafer communication along hypergraph-optimized paths. Across diverse workloads, HyperWafer delivers average speedups of 979.97x, 125.23x, 12.14x, and 5.14x over state-of-the-art CPU, GPU, FPGA, and WSC SpGEMM implementations.
In this work, we present HyperWafer, the first communication-aware SpGEMM framework for WSCs, combining a hypergraph-guided execution model with dedicated architectural support. HyperWafer captures SpGEMM's inherently high-order dataflow dependencies, which arise from multiway row sharing and overlapping reduction scopes, using a weighted hypergraph abstraction that enables communication-centric partitioning and topology-aware mapping aligned with the wafer's physical bandwidth distribution. To efficiently realize this model, HyperWafer integrates a sparsity-aware SpGEMM execution engine that sustains high per-PE throughput under irregular workloads together with a lightweight, congestion-sensitive runtime routing substrate that preserves effective on-wafer communication along hypergraph-optimized paths. Across diverse workloads, HyperWafer delivers average speedups of 979.97x, 125.23x, 12.14x, and 5.14x over state-of-the-art CPU, GPU, FPGA, and WSC SpGEMM implementations.
Event Type
Research Manuscript
TimeMonday, July 2712:16pm - 12:30pm PDT
LocationMtg Room 202C