Presentation
LRTA: Routability-Driven 3D-Aware Track Assignment with Layer Reassignment
DescriptionAs the critical stage in chip design, routing comprises global routing and detailed routing, with track assignment (TA) serving as an intermediate step to bridge the two routing phases. However, existing methods consider only 2D mismatches and overlook 3D coordination, resulting in degraded routing quality. This paper proposes LRTA, a routability-driven 3D-aware track assignment framework with layer reassignment to coordinate the resources across layers while preserving connectivity. In addition, a GPU-accelerated TA scheme is proposed to construct candidates and dynamically assign tracks, enabling efficient concurrent evaluation. Experimental results demonstrate that, compared with existing works, the proposed LRTA achieves significant improvements in routability estimation with shorter runtime.
Event Type
Research Manuscript
TimeTuesday, July 284:54pm - 5:06pm PDT
LocationMtg Room 202AB