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Transsyn: Scalable, Area-Oriented Transistor Network Synthesis via Cut-Based Mapper with SAT-Based Refinement

DescriptionSAT-based transistor network synthesis delivers optimal, minimum-transistor designs but faces exponential complexity, making it impractical for large circuits. This paper introduces TransSyn, a scalable transistor network synthesizer that brings the benefits of SAT-based synthesis to the macro-cell scale through a novel two-stage framework. First, a cut-based global synthesis stage reformulates the task as a cut-based mapping problem, rapidly decomposing the design into smaller, manageable sub-problems. This ensures scalability and produces a high-quality network in seconds. Then, a SAT-based detailed synthesis stage refines this network by systematically identifying and re-optimizing merged subcircuits across cut boundaries using a SAT-based approach, recapturing lost optimization opportunities. Experiments demonstrate that TransSyn significantly outperforms previous methods, achieving 11.2% and 10% reductions in transistor count compared to graph-based and hybrid-based approaches, respectively. Furthermore, when integrated with a transistor-level placer, TransSyn breaks the library and cell boundaries, yielding up to a 48.8% area reduction compared to conventional cell-based designs. TransSyn demonstrates its capability for scalable, high-quality transistor-network synthesis, successfully bridging the gap between the optimality of SAT-based synthesis and the practical demands of large-scale cell design.

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