Presentation
Cell-Structure-Independent Transistor-Level Placement and MOL-Aware Routing Framework Beyond the Standard-Cell Paradigm
DescriptionStandard-cell-based design has long been the dominant approach in VLSI design, providing scalability and compatibility with established EDA tools. However, as design technology co-optimization (DTCO) becomes increasingly important at advanced process nodes, the fixed structure of standard cells limits the ability to optimize wirelength and area effectively, imposing a critical bottleneck at the Middle-of-Line (MOL) layers. In this context, dense pin access and M0 routing resources, critical for alleviating congestion on higher metal layers, are rigidly constrained by the cell boundary. A more flexible approach is to directly place transistors on the design canvas and perform routing at the transistor level, enabling physical-level optimization beyond the logic-level constraints imposed by standard-cell design. This work introduces a novel framework featuring cell-structure-independent transistor-level placement coupled with an MOL-aware routing engine. Experimental results demonstrate that the proposed framework achieves considerable improvements in wirelength and design area compared to the commercial standard-cell-based design tool and state-of-the-art transistor-level work.
Event Type
Research Manuscript
TimeWednesday, July 293:42pm - 3:54pm PDT
LocationMtg Room 202AB