Presentation
Safegen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety
DescriptionTraditional simulation-based fault analysis tends to be overly conservative and fails to reflect true fault criticality.
This paper presents SafeGen, an LLM-driven, formal-verification-assisted framework for functional-safety-oriented fault criticality assessment.
SafeGen employs large language models with a Hyper Knowledge Graph (HyperKG) to extract verifiable specifications and to evaluate their importance for overall system safety.
The HyperKG is then extended with register-transfer level information to guide the generation of Functional Safety Assertions.
A gate-to-RTL fault-mapping mechanism supporting both stuck-at and bridging faults, combined with formal property verification, enables semantic-level fault criticality grading. A digital–physical co-simulation platform for a field-oriented control system validates SafeGen.
This paper presents SafeGen, an LLM-driven, formal-verification-assisted framework for functional-safety-oriented fault criticality assessment.
SafeGen employs large language models with a Hyper Knowledge Graph (HyperKG) to extract verifiable specifications and to evaluate their importance for overall system safety.
The HyperKG is then extended with register-transfer level information to guide the generation of Functional Safety Assertions.
A gate-to-RTL fault-mapping mechanism supporting both stuck-at and bridging faults, combined with formal property verification, enables semantic-level fault criticality grading. A digital–physical co-simulation platform for a field-oriented control system validates SafeGen.
Event Type
Research Manuscript
TimeWednesday, July 292:47pm - 3:00pm PDT
LocationMtg Room 202C
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