Presentation
RL4HDL: Code Diversity Guided FPGA Logic Synthesis Compiler Testing Via Reinforcement Learning
DescriptionLogic synthesis compilers play an indispensable role in FPGA design, translating register-transfer-level (RTL) descriptions into gate-level netlists. Defects in these compilers may compromise the security of the final hardware implementations. Existing testing methods often produce redundant test cases, which limits their ability to effectively explore compiler defects. To address this problem, we propose RL4HDL, a new method that uses reinforcement learning to guide logic synthesis compiler testing. Comprehensive experiments conducted over a three-month period demonstrate the practical effectiveness of our approach: we discovered 20 unique defects, including 12 previously unreported ones, all of which have been confirmed by the official developers.
Event Type
Research Manuscript
TimeTuesday, July 283:56pm - 4:10pm PDT
LocationMtg Room 201B