Presentation
LLMVA: LLMs Empowered Verilog-A Iterative for MRAM Design Technology Co-Optimization
DescriptionEmerging device characteristics modeling is indispensable for potential circuit design integration. In the modeling process, the Verilog-A language is employed, leveraging the physical parameters and test results of the device. This work demonstrates the large language model (LLM) empowered Verilog-A iterative (LLMVA) for the modeling process of spin-transfer-torque magnetic-tunnel-junction (STT-MTJ). LLM enhances the quick interaction with device-level characteristics and circuit-level indicators, and realize design technology co-optimization (DTCO). In macro level, the 4-Mb 28-nm magnetic-random-access-memory (MRAM) macro is designed and then tape-out. To the best of the authors' knowledge, this is the first work to use LLM for device modeling and MRAM DTCO. The iterative test results show that the deviation between Front-test/Post-test results of MTJ does not exceed 9.2%, proving the effectiveness of the proposed LLMVA modeling process. With the proposed LLMVA agent, we have decreased our designer and time cost by about 50%.
Event Type
Research Manuscript
TimeTuesday, July 281:42pm - 1:55pm PDT
LocationMtg Room 101B