Presentation
Hierarchical Boundary Recovery: Overcoming Synthesis Obscurity via SAT Sweeping
DescriptionIn the integrated circuit design flow, a high-level specification is synthesized into a gate-level netlist. However, this synthesis often results in the loss of the association between the high-level and gate-level designs. Maintaining signal correspondences between these two levels is crucial for preserving the design hierarchy, which in turn facilitates design debugging, engineering change orders (ECOs), cross-abstraction-level model training, and other synthesis and verification tasks. In this work, we present an automated approach for recovering the hierarchical boundaries of high-level components in gate-level netlists, even in cases where the synthesis process has completely removed the original boundary signals. The method is implemented as an open-source tool, and the experimental results demonstrate its robustness in recovering hierarchical boundaries. Our results may benefit various potential applications in synthesis and verification.
Event Type
Research Manuscript
TimeMonday, July 2712:16pm - 12:30pm PDT
LocationMtg Room 201B
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