Presentation
GRACE: A Ground Plane Generation and Re-Routing Aware Co-Design Engine
DescriptionIn modern high-density Printed Circuit Board (PCB) design, the conventional sequential workflow often leads to a fractured ground plane, compromising signal integrity and system performance. Existing Electronic Design Automation (EDA) tools passively fill unoccupied space with copper post-routing, lacking the ability to modify wire segments to improve ground plane continuity. In this paper, we propose A Ground Plane Generation and Re-routing Aware Co-design Engine, a novel, topology-aware framework that fundamentally shifts the paradigm from passive filling to an integrated co-design process. GRACE formulates ground plane generation as an optimization problem tightly coupled with automated rerouting. It partitions the layout into copper-pourable regions and blockages, and abstracts this into a novel weighted graph model, the Ground Plane Graph (GPGraph). We then formulate an Integer Linear Programming (ILP) problem on the GPGraph to identify a globally optimal set of blockages to eliminate. By strategically rerouting a minimal number of power & signal wire segments, GRACE merges isolated copper islands to create a maximum and contiguous ground plane. Experimental results demonstrate that GRACE drastically increases the area of the ground plane by an average of 33.06% and reduces the number of the ground plane polygons by 54.34% compared to open-source EDA tools. Moreover, our method achieves a significant speed-up over manual refinement while attaining an equivalent ground-plane area and number of ground plane polygons. To the best of our knowledge, this is the first work to automate ground plane unification through an integrated rerouting-aware co-design methodology.
Event Type
Research Manuscript
TimeTuesday, July 284:30pm - 4:42pm PDT
LocationMtg Room 203AB