Presentation
SpArC: Sparse Tensor Accelerator Compilation with Scheduling and Mapping
DescriptionSparse tensor computation is widely used in deep learning and scientific computing, but its irregular computation and memory access patterns pose significant challenges for general-purpose accelerators such as GPUs and NPUs. FPGAs, owing to their reconfigurability, are inherently well-suited for handling sparse workloads. However, existing point-based manual design paradigms severely limit the performance potential of reconfigurable hardware across diverse sparse scenarios.
To address this, we propose SpArC—an automated compilation framework for sparse tensor computation that automatically generates high-performance FPGA accelerators.
SpArC consists of:(1) a primitive-based DSL serving as the design specification for sparse accelerators, providing a unified abstraction of data formats, iteration pattern, and hardware mapping strategies;(2) a two-stage mapping mechanism centered around sparse meta-operations, enabling arbitrary sparse dataflows to be efficiently mapped to hardware micro-architectures; and(3) a heuristic design space exploration method for joint software–hardware optimization.Experimental results show that SpArC can automatically generate FPGA accelerators for typical sparse workloads such as SpMSpV, Plus3, and SpMM. On the SuiteSparse benchmark dataset,for SpMSpV workloads, SpArC achieves 31.7×–130.4× performance improvement over automated frameworks such as ScaleHLS and Allo. On the same SuiteSparse SpMSpV workloads running on CPU platforms, SpArC further achieves 10.8x–34.7× speedup over TACO and 1.03x–1.89x speedup over MKL.
To address this, we propose SpArC—an automated compilation framework for sparse tensor computation that automatically generates high-performance FPGA accelerators.
SpArC consists of:(1) a primitive-based DSL serving as the design specification for sparse accelerators, providing a unified abstraction of data formats, iteration pattern, and hardware mapping strategies;(2) a two-stage mapping mechanism centered around sparse meta-operations, enabling arbitrary sparse dataflows to be efficiently mapped to hardware micro-architectures; and(3) a heuristic design space exploration method for joint software–hardware optimization.Experimental results show that SpArC can automatically generate FPGA accelerators for typical sparse workloads such as SpMSpV, Plus3, and SpMM. On the SuiteSparse benchmark dataset,for SpMSpV workloads, SpArC achieves 31.7×–130.4× performance improvement over automated frameworks such as ScaleHLS and Allo. On the same SuiteSparse SpMSpV workloads running on CPU platforms, SpArC further achieves 10.8x–34.7× speedup over TACO and 1.03x–1.89x speedup over MKL.
Event Type
Research Manuscript
TimeMonday, July 273:30pm - 3:42pm PDT
LocationMtg Room 202C
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