Presentation
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
DescriptionFunctional verification accounts for over 50% of the IC development lifecycle, making SystemVerilog Assertions (SVAs) indispensable for rigorous digital chip verification. However, manual SVA authoring is labor-intensive and error prone. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. The AgentBridge platform facilitates systematic data generation, augmentation, and validation, decomposing complex verification processes into modular, verifiable subtasks. ChatSVA achieves syntax and function pass rates of 98.66% and 96.12%, averaging 139.5 SVAs per design with 82.50% function coverage. A ChatSVA web service is publicly available.
Event Type
Research Manuscript
TimeMonday, July 273:30pm - 3:42pm PDT
LocationMtg Room 101A
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