Presentation
A Levelized Load-Balanced and Structure-Adaptive GPU LU Factorization Method for Circuit Simulation
DescriptionAs integrated circuit (IC) designs grow increasingly complex and transistor counts per chip exceed ten billion, post-layout SPICE simulations involve large-scale sparse linear systems, severely degrading simulation efficiency
Current GPU acceleration methods, despite their promise, struggle with efficient load balancing and resource utilization, which restricts their effectiveness in ultra-large-scale circuit simulations.
In this paper, we propose a levelized load-balanced and structure-adaptive LU factorization framework for GPU-based circuit simulation.
Our method improves resource utilization and parallel efficiency by introducing computation-balanced dependency level partitioning, adaptive resource allocation, and a hybrid matrix indexing mechanism.
These strategies ensure that both the memory and computational resources of the GPU are fully leveraged.
We demonstrate significant acceleration over existing methods, achieving a 2.1X speedup compared to GLU3.0 and a 5.2X speedup over 16-thread PARDISO on circuit sparse matrices ranging from thousands to millions of dimensions.
Additionally, our framework has been successfully integrated into the open-source SPICE simulator Ngspice, accelerating circuit simulations with promising results and showcasing its potential for large-scale IC design verification.
Current GPU acceleration methods, despite their promise, struggle with efficient load balancing and resource utilization, which restricts their effectiveness in ultra-large-scale circuit simulations.
In this paper, we propose a levelized load-balanced and structure-adaptive LU factorization framework for GPU-based circuit simulation.
Our method improves resource utilization and parallel efficiency by introducing computation-balanced dependency level partitioning, adaptive resource allocation, and a hybrid matrix indexing mechanism.
These strategies ensure that both the memory and computational resources of the GPU are fully leveraged.
We demonstrate significant acceleration over existing methods, achieving a 2.1X speedup compared to GLU3.0 and a 5.2X speedup over 16-thread PARDISO on circuit sparse matrices ranging from thousands to millions of dimensions.
Additionally, our framework has been successfully integrated into the open-source SPICE simulator Ngspice, accelerating circuit simulations with promising results and showcasing its potential for large-scale IC design verification.
Event Type
Research Manuscript
TimeMonday, July 272:34pm - 2:47pm PDT
LocationMtg Room 202AB
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