Presentation
DIA-CIM: A Dynamic Iterative Aggregation Graph Neural Network and Its Hardware Co-Design for Energy-Efficient Graph Processing
DescriptionDynamic-iterative aggregation (DIA) in graph neural networks updates node states sequentially and asynchronously. This expands the receptive field without adding layers and improves accuracy-per-operation versus layer-synchronous models. However, DIA introduces fine-grained serial dependencies and highly irregular sparse traffic that undermine conventional SIMD/accelerator designs. We present DIA-CIM, a 28-nm compute-in-memory (CIM) macro co-designed for DIA. DIA-CIM employs a CSR-driven, output-stationary dataflow to keep partial sums local while streaming edges, a sparsity-priority BF16 pipeline that exploits bit/value sparsity. Fabricated in 28-nm CMOS, DIA-CIM reaches 60.01 TFLOPS/W. On representative DIA workloads, it delivers >3.56 × lower energy and >2.32 × lower latency.
Event Type
Research Manuscript
TimeMonday, July 2711:10am - 11:23am PDT
LocationMtg Room 203AB
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