Presentation
Noisexplore: A Device-Aware Hierarchical Noise Modeling and DTCO Framework for Analog In-Pixel Computing Architectures
DescriptionAnalog in-Pixel computing (IPC) enables energy-efficient edge AI but faces critical noise challenges limiting computing accuracy. Existing design flows lack comprehensive device-aware noise modeling and cross-layer optimization. We introduce NoiseXplore, the first end-to-end design-technology co-optimization framework integrating: (1) physics-grounded noise models (thermal, shot, RTN, device mismatch); (2) device-aware SNR estimation and neural network co-simulation; (3) circuit-level performance modeling integrated into NeuroSim; and (4) automated Bayesian DTCO for multidimensional design space exploration. Demonstrated on noise-sensitive 1T FDSOI-based IPC, optimized configurations achieve 50 fps with 86.8% CIFAR-10 classification accuracy on a three-class subset (airplane/car/ship).
Event Type
Research Manuscript
TimeMonday, July 2710:56am - 11:10am PDT
LocationMtg Room 203AB
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