Presentation
From Characterization to Microarchitecture: Designing an Elegant and Reliable BFP-Based NPU
DescriptionBFP is emerging as an attractive data format for edge NPUs, combining wide dynamic range with high hardware efficiency. However, its behavior under hardware faults and its suitability for safety-critical deployments remain largely underexplored. Here, we present the first in-depth empirical reliability study of BFP-based NPUs. Using RTL-level fault injection on NPUs, our bit- and path-level analysis reveals pronounced heterogeneous vulnerabilities and shows that the conventional end-to-end check becomes largely ineffective under nonlinear block scaling. Guided by these insights, we design a fault-tolerant BFP-based NPU microarchitecture that aligns the BFP computational semantics with reliability constraints. The design uses a row/column-wise blocking strategy to decouple the fixed-point mantissa computations from the scalar exponent path, and introduces ultra-lightweight protection mechanisms for each. Experimental results demonstrate that our design achieves near–dual modular redundancy reliability with only 3.55% geometric mean performance overhead and less than 2% hardware cost.
Event Type
Research Manuscript
TimeTuesday, July 2810:43am - 10:56am PDT
LocationMtg Room 202C