Presentation
Gearls: Generalizable Reinforcement Learning Framework for Logic Optimization via Policy Similarity Metric
DescriptionLogic optimization is a crucial step in digital circuit synthesis, directly impacting the final power, performance, and area (PPA) of integrated circuits. While reinforcement learning (RL) has shown promise in generating high-quality optimization flows, its limited generalization ability necessitates retraining for each new circuit, hindering practical deployment. To address this, we propose a novel RL-based framework that achieves strong zero-shot generalization across unseen circuits. Our work introduces three key innovations: (1) logic cone extraction to reduce input complexity and enable efficient reward estimation; (2) a cut-weighting mechanism that models global timing effects from local subgraphs; and (3) the integration of Policy Similarity Metric (PSM) to enhance state representation and improve zero-shot transfer. Evaluated on a set of unseen benchmark circuits, Our work outperforms state-of-the-art methods—achieving 31.7% lower worst negative slack (WNS) and 32.5% lower total negative slack (TNS)—while running in only 13% of the time required by prior approaches. This work demonstrates that generalizable RL can enable fast, high-quality logic optimization without circuit-specific retraining.
Event Type
Research Manuscript
TimeTuesday, July 283:43pm - 3:56pm PDT
LocationMtg Room 201B
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