Presentation
Is EDA AI Delivering on Its ROI Promise?
DescriptionMachine Learning (ML) and Reinforcement Learning (RL) are now standard in EDA, and Generative and Agentic AI is growing rapidly. Engineering leaders now face a critical question: beyond the hype, what is the actual Return on Investment (ROI) in chip design? This panel brings together industry experts to share real stories and measure the true value of AI over the past few years. We cover the full workflow, from HLS to digital implementation and verification.
Speed-ups vs. productivity boosts: We distinguish between raw speed improvements, such as faster simulations and verification, and true productivity gains from GenAI tools used for copilot-style documentation assistance, tool setup, and debugging. The discussion moves away from simple metrics (e.g., lines of code per hour) to the real drivers of ROI: reducing design cycles and getting to working silicon faster.
Junior vs. senior chip designers: The panel will also examine the impact across different experience levels. For juniors, AI speeds up work but risks weakening their grasp of the basics. For seniors, does AI handle repetitive tasks, or does it turn these senior architects into "error checkers" for AI-generated code? We compare cases where AI saved weeks of effort with those where poor code or settings required expensive manual fixes, and we discuss the strategies (e.g., data flywheel, model fine-tuning, human training) needed to reduce these risks.
AI Agents and MCP: Finally, we discuss the shift to autonomous EDA AI Agents that can automate certain flows and, in the future, drive full-flow automations. Since the current roadblock is that disconnected tools stall progress, Model Context Protocol (MCP) and Agent-to-Agent (A2A) are emerging as standards for agentic workflows and, potentially, for RTL-to-GDSII flows. We debate whether this "glue" can truly work, the investment needed to build it, whether fully autonomous workflows are realistic or just a dream, and how they unlock further ROI.
Speed-ups vs. productivity boosts: We distinguish between raw speed improvements, such as faster simulations and verification, and true productivity gains from GenAI tools used for copilot-style documentation assistance, tool setup, and debugging. The discussion moves away from simple metrics (e.g., lines of code per hour) to the real drivers of ROI: reducing design cycles and getting to working silicon faster.
Junior vs. senior chip designers: The panel will also examine the impact across different experience levels. For juniors, AI speeds up work but risks weakening their grasp of the basics. For seniors, does AI handle repetitive tasks, or does it turn these senior architects into "error checkers" for AI-generated code? We compare cases where AI saved weeks of effort with those where poor code or settings required expensive manual fixes, and we discuss the strategies (e.g., data flywheel, model fine-tuning, human training) needed to reduce these risks.
AI Agents and MCP: Finally, we discuss the shift to autonomous EDA AI Agents that can automate certain flows and, in the future, drive full-flow automations. Since the current roadblock is that disconnected tools stall progress, Model Context Protocol (MCP) and Agent-to-Agent (A2A) are emerging as standards for agentic workflows and, potentially, for RTL-to-GDSII flows. We debate whether this "glue" can truly work, the investment needed to build it, whether fully autonomous workflows are realistic or just a dream, and how they unlock further ROI.
Organizer
Event Type
DAC Pavilion Panel
TimeTuesday, July 284:00pm - 4:45pm PDT
LocationDAC Pavilion, Exhibit Floor