Presentation
From RTL to Reality: Building Security into the Silicon Lifecycle
DescriptionSecurity can no longer be treated as a late-stage feature, a firmware patch, or a checklist item before tapeout. As chips become more complex, more connected, and more dependent on third-party IP, advanced packaging, global supply chains, and long field lifetimes, trust must be established and maintained across the entire silicon lifecycle: from architecture and RTL design through verification, implementation, manufacturing, provisioning, deployment, monitoring, and update.
This panel will examine what it means to build a secure silicon lifecycle in practice. Where should security requirements be captured? Can security verification become part of mainstream EDA signo? How should teams reason about third-party IP, FPGA bitstreams, hardware roots of trust, device identity, key provisioning, and post-deployment assurance?And who is accountable when a vulnerability appears after a device has shipped?
AI introduces a new silicon-security paradox: it can help designers create hardware faster than ever, potentially scaling vulnerabilities across complex SoCs, while also giving verification and security teams new ways to detect, explain, and remediate those vulnerabilities before tapeout.
Bringing together perspectives from academia, security technology providers, and industry practitioners, this discussion will ask whether the industry needs new tools, standards, processes, or ownership models to make security a continuous discipline across the lifetime of a chip.
This panel will examine what it means to build a secure silicon lifecycle in practice. Where should security requirements be captured? Can security verification become part of mainstream EDA signo? How should teams reason about third-party IP, FPGA bitstreams, hardware roots of trust, device identity, key provisioning, and post-deployment assurance?And who is accountable when a vulnerability appears after a device has shipped?
AI introduces a new silicon-security paradox: it can help designers create hardware faster than ever, potentially scaling vulnerabilities across complex SoCs, while also giving verification and security teams new ways to detect, explain, and remediate those vulnerabilities before tapeout.
Bringing together perspectives from academia, security technology providers, and industry practitioners, this discussion will ask whether the industry needs new tools, standards, processes, or ownership models to make security a continuous discipline across the lifetime of a chip.
Event Type
DAC Pavilion Panel
TimeMonday, July 272:00pm - 2:45pm PDT
LocationDAC Pavilion, Exhibit Floor