Presentation
GenAI for Aerospace and Defense Silicon: Design Authority or Design Assist?
DescriptionGenerative AI is increasingly being applied across electronic design automation (EDA), from architecture exploration to RTL and physical design. At the same time, aerospace and defense chip designs are becoming more complex, with growing reliance on heterogeneous integration, chiplet-based architectures, and advanced packaging to support AI-driven workloads such as sensor fusion and real-time processing. These systems are often tightly coupled to larger platforms and operating environments, placing strong emphasis on architectural choices, integration boundaries, data movement, and security assumptions across chiplet and packaging interfaces early in design. They are also expected to operate reliably under harsh environmental conditions and over long service lifetimes, which further constrains architectural flexibility and integration tradeoffs.
This panel explores how these conditions shape the role of GenAI in aerospace and defense chip design. Panelists will discuss where GenAI fits within chip architecture, integration, and implementation tasks, and whether it can influence decisions that affect system behavior, performance metrics, and integration complexity. The discussion will also examine constraints on data access and sharing, the use of synthetic data, the interaction between GenAI-driven design approaches and emerging trends such as chiplets and 3D heterogeneous integration, the trustworthiness and security of GenAI-based design tools themselves, and the role of emerging GenAI training and optimization approaches, such as iterative self-refinement and multi-step reinforcement learning, in chip design.
1. In which stages of aerospace and defense chip design has GenAI demonstrated practical value, and which stages remain dominated by conventional EDA methods?
2. Can GenAI influence early architectural and integration decisions, such as chiplet partitioning, or does it primarily operate after these choices are set?
3. How does chiplet-based and 3D integration change the role of GenAI across the chip design flow?
4. How do data availability and data sensitivity affect the application of GenAI in defense-oriented chip design, and what role can synthetic data realistically play in this context?
5. Do chiplet-based architectures introduce security assumptions that GenAI struggles to capture at design time, and what security risks arise from relying on GenAI systems that cannot themselves be fully trusted?
6. What technical risks associated with GenAI in chip design deserve the most attention in aerospace and defense applications, and how can these risks be detected, bounded, or mitigated?
7. How might broader adoption of GenAI influence the skill sets required for aerospace and defense chip designers?
This panel explores how these conditions shape the role of GenAI in aerospace and defense chip design. Panelists will discuss where GenAI fits within chip architecture, integration, and implementation tasks, and whether it can influence decisions that affect system behavior, performance metrics, and integration complexity. The discussion will also examine constraints on data access and sharing, the use of synthetic data, the interaction between GenAI-driven design approaches and emerging trends such as chiplets and 3D heterogeneous integration, the trustworthiness and security of GenAI-based design tools themselves, and the role of emerging GenAI training and optimization approaches, such as iterative self-refinement and multi-step reinforcement learning, in chip design.
1. In which stages of aerospace and defense chip design has GenAI demonstrated practical value, and which stages remain dominated by conventional EDA methods?
2. Can GenAI influence early architectural and integration decisions, such as chiplet partitioning, or does it primarily operate after these choices are set?
3. How does chiplet-based and 3D integration change the role of GenAI across the chip design flow?
4. How do data availability and data sensitivity affect the application of GenAI in defense-oriented chip design, and what role can synthetic data realistically play in this context?
5. Do chiplet-based architectures introduce security assumptions that GenAI struggles to capture at design time, and what security risks arise from relying on GenAI systems that cannot themselves be fully trusted?
6. What technical risks associated with GenAI in chip design deserve the most attention in aerospace and defense applications, and how can these risks be detected, bounded, or mitigated?
7. How might broader adoption of GenAI influence the skill sets required for aerospace and defense chip designers?
Event Type
Research Panel
TimeWednesday, July 291:30pm - 3:00pm PDT
LocationMtg Room 104A
AI