Presentation
Who Holds the Upper Hand: Electrical or Photonic Links in Scaled-out Chiplet Systems?
DescriptionChiplet-based integration has become a driving force behind the scale-up of leading systems in high-performance computing (HPC) and artificial intelligence (AI). This migration introduces a spectrum of design choices and trade-offs, particularly in inter-chiplet signaling and interconnection. As chiplet systems scale out to hundreds or even thousands of compute and memory tiles, a new ecosystem is rapidly taking shape, spanning advanced packaging and substrate technologies to novel signaling protocols and physical interfaces.
While high-speed electrical links remain the workhorse of today's chiplet architectures, photonic interconnects present a compelling alternative, promising massive bandwidth and energy efficiency over longer distances. Yet, photonics still faces significant challenges: integration complexity, electro-optical conversion overhead, and thermal sensitivity. Electrical links, in contrast, offer greater maturity, lower cost, and proven scalability.
The question now stands: as chiplet systems continue to scale, will photonic links become essential, or will electrical interconnects maintain their dominance?
While high-speed electrical links remain the workhorse of today's chiplet architectures, photonic interconnects present a compelling alternative, promising massive bandwidth and energy efficiency over longer distances. Yet, photonics still faces significant challenges: integration complexity, electro-optical conversion overhead, and thermal sensitivity. Electrical links, in contrast, offer greater maturity, lower cost, and proven scalability.
The question now stands: as chiplet systems continue to scale, will photonic links become essential, or will electrical interconnects maintain their dominance?
Event Type
Research Panel
TimeTuesday, July 281:30pm - 3:00pm PDT
LocationMtg Room 104A
Design