Presentation
Neural Subgraph Matching for Hardware Decompilation in Gate-Level Netlists
DescriptionModern IC globalization and automated synthesis often produce flattened netlists that obscure design intent, complicating hardware security analysis and reverse engineering. Traditional decompilation methods based on exact subgraph isomorphism or fixed libraries are computationally expensive and struggle to detect unseen logic patterns. We propose a self-supervised neural subgraph matching framework that decomposes netlists into k-hop networks and embeds them into a latent order space to effectively identify repeated arithmetic primitives. Experiments on adders and multipliers show that the method generalizes from small training circuits to larger designs, enabling scalable recovery of high-level behavior from gate-level netlists.
Event Type
Late Breaking Results
TimeMonday, July 275:19pm - 5:22pm PDT
LocationExhibit Hall