Presentation
Late Breaking Results: HUSH: Silencing Inter-Core Interference in Real-Time Cache Analysis
DescriptionStatic worst-case execution time (WCET) analysis for multicore real-time systems remains pessimistic because write-invalidate coherence perturbs remote cache states at run time, preventing per-core hit/miss classification. We present HUSH, a write-update coherence that silences interference while bounding update traffic with time-based self-invalidation. The timeout defines a sharing window and is tuned offline to balance predictability and performance. On SPLASH-2 in gem5, HUSH reduces worst-case total memory latency (WCML) by 30.7x and 8.4x vs. PMSI and PENDULUM*, while keeping average performance within 1.17x of MSI baseline.
Event Type
Late Breaking Results
TimeMonday, July 276:21pm - 6:24pm PDT
LocationExhibit Hall