Presentation
DScNMP: A Dataflow Scheduling for the Precision-Scalable Near-Memory Processing Microarchitecture
DescriptionNear-memory processing (NMP) mitigates the overhead of host-memory data movement while maintaining efficient data access.
We introduce DScNMP, an architecture-dataflow co-design that employs dataflow scheduling to optimize NMP executions.
DScNMP incorporates dynamic workload scheduling, intra-cycle coordinated control, and state supervision units, ensuring efficient resource management.
Evaluation results show that DScNMP, occupies 0.006384 mm^2 in 14 nm, achieves 2.7× lower data access latency, up to 8.9× and 4.9× fewer cycles for external data movement and memory-bound workloads, respectively, and delivers 2.4× higher multiply-accumulate efficiency than Armv8.1-M.
We introduce DScNMP, an architecture-dataflow co-design that employs dataflow scheduling to optimize NMP executions.
DScNMP incorporates dynamic workload scheduling, intra-cycle coordinated control, and state supervision units, ensuring efficient resource management.
Evaluation results show that DScNMP, occupies 0.006384 mm^2 in 14 nm, achieves 2.7× lower data access latency, up to 8.9× and 4.9× fewer cycles for external data movement and memory-bound workloads, respectively, and delivers 2.4× higher multiply-accumulate efficiency than Armv8.1-M.
Event Type
Late Breaking Results
TimeMonday, July 275:42pm - 5:45pm PDT
LocationExhibit Hall