Presentation
Late Breaking Results: Physics-Aware Diffusion Framework for Transistor-Level Placement Beyond Standard-Cell Boundary
DescriptionAs conventional standard-cell methodologies increasingly limit Design Technology Co-Optimization (DTCO) in advanced nodes, direct transistor-level placement emerges as a crucial solution for minimizing wirelength and area. However, existing analytical placers optimize continuous coordinates, struggling to capture the strictly discrete and directional nature of active breaks.
To overcome this, we propose a physics-aware generative framework featuring a novel Augmented Split-Graph to explicitly model complex active break constraints. By employing a continuous latent diffusion process that deterministically decodes into discrete Sequence Pairs, our method bridges continuous generative modeling and discrete physical constraints, guaranteeing strictly overlap-free layouts. Experimental results demonstrate that our framework significantly outperforms a leading commercial standard-cell-based baseline, achieving a 12.4\% reduction in average wirelength, a 13.4\% increase in active-sharing count, and a 7.4\% overall reduction in layout area.
To overcome this, we propose a physics-aware generative framework featuring a novel Augmented Split-Graph to explicitly model complex active break constraints. By employing a continuous latent diffusion process that deterministically decodes into discrete Sequence Pairs, our method bridges continuous generative modeling and discrete physical constraints, guaranteeing strictly overlap-free layouts. Experimental results demonstrate that our framework significantly outperforms a leading commercial standard-cell-based baseline, achieving a 12.4\% reduction in average wirelength, a 13.4\% increase in active-sharing count, and a 7.4\% overall reduction in layout area.
Event Type
Late Breaking Results
TimeMonday, July 275:00pm - 5:03pm PDT
LocationExhibit Hall
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