Presentation
Late Breaking Results: Scalable OARSMT Generation via Predictive Topological Reduction in VLSI Routing
DescriptionEfficient OARSMT construction is a critical bottleneck for modern VLSI routing. Current solutions either achieve high speed but ignore obstacles, or guarantee legality at the expense of prohibitive runtimes. In this paper, we introduce a scalable framework that predictively compresses the routing search space without sacrificing wirelength quality. We first present a learning-guided candidate pruning to condense the obstacle-expanded graph into a set of high-confidence Steiner candidates. Then, we establish a novel Delaunay-driven topological sparsification that geometrically confines any optimal obstacle-avoiding rectilinear tree to a linear-size subspace. Evaluations on extreme-density benchmarks demonstrate a $1.63\times$ speedup and a 3.2\% wirelength reduction over the state-of-the-art solver. Furthermore, integrating our framework into TritonRoute-WXL reduces the total routing runtime by 7.0\% and wirelength by 0.3\% on ICCAD 2019 benchmarks, without introducing any additional DRC violations.
Event Type
Late Breaking Results
TimeMonday, July 276:04pm - 6:08pm PDT
LocationExhibit Hall