Presentation
Late Breaking Results: Nano-TSV Assignment for Backside Power Delivery Network Designs Considering Stress and IR-Drop Effects
DescriptionAs resistance and routing congestion intensify at advanced nodes, backside power delivery networks (BSPDNs) have emerged to offload power routing from congested frontside metal. In BSPDNs, nano-through-silicon vias (n-TSVs) bridge backside power layers to frontside transistors, and their placement critically impacts IR-drop, thermomechanical stress, and manufacturability. Unlike traditional frontside PDNs, where TSV candidates can be placed in general whitespace, BSPDN n-TSVs are constrained to buried power rail (BPR) locations, and their stress effects are non-negligible. Prior staggered assignment schemes mitigate congestion but introduce manufacturing complexity and excessive via counts. We present the first IR-drop-aware n-TSV optimization flow for BSPDNs under n-TSV density constraints that enhance packaging manufacturability. We provide a mixed integer linear programming (MILP) formulation based on our circuit model for backside power delivery networks. We use efficient model transformation and legalization methods to obtain our final assignment solutions. Compared with the state-of-the-art staggered assignment method, we reduce the required number of n-TSVs by an average of 56.68% to satisfy the given IR-drop constraints within a reasonable runtime.
Event Type
Late Breaking Results
TimeMonday, July 276:40pm - 6:43pm PDT
LocationExhibit Hall
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