Presentation
Late Breaking Results: Merge-Aware Placement and DP-Based Wave Propagation Routing for Scalable Flip-FET Cell Layout Synthesis
DescriptionAs transistor scaling advances beyond the 3 nm node, the Flip-FET (FFET) architecture has emerged to provide dual-sided pin accessibility. However, ensuring routable dual-sided connectivity in compact FFET standard cells remains challenging. This work presents a scalable FFET standard cell layout synthesis framework that jointly optimizes transistor placement, pin accessibility, and in-cell routing through two tightly coupled optimization phases: a satisfiability modulo theories (SMT)-based merge-aware transistor placement phase, followed by a dynamic programming (DP)-based wave propagation routing phase that integrates dynamic pin assignment. Experimental results on 3.5T FFET cells show reductions of 5%, 10%, and 22% in cell width, via count, and wirelength over DAC-25, and 1%, 6%, and 14% over ASPDAC-26. Furthermore, the proposed framework successfully routes all 2.5T FFET cells, achieving up to 27% area reduction compared to the corresponding 3.5T designs.
Event Type
Late Breaking Results
TimeMonday, July 276:37pm - 6:40pm PDT
LocationExhibit Hall
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