Presentation
Late Breaking Results: EIV-Aware Backside PDN Synthesis Under Strict nTSV Spacing Constraints
DescriptionBackside power delivery networks (BSPDNs) alleviate front-side routing congestion, yet they introduce new challenges, including high resistance of buried power rails (BPRs) and nano-through-silicon vias (TSVs), as well as stringent TSV spacing constraints. This paper presents the first power-aware BSPDN synthesis framework that simultaneously accounts for post-placement power demand and strict TSV spacing rules. The proposed framework incorporates a lightweight resistive-network model to accurately evaluate effective instance voltage (EIV) and employs a three-phase optimization strategy to strategically align TSV allocation with power-intensive regions. Experimental results show that our approach reduces the maximum EIV drop by up to 25\% compared with a state-of-the-art post-placement BSPDN method.
Event Type
Late Breaking Results
TimeMonday, July 275:58pm - 6:01pm PDT
LocationExhibit Hall
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