Presentation
Physical Signoff at Scale: Tackling TSV, Interposer, and ESD in 3DIC Systems
DescriptionThe proliferation of 3D Integrated Circuits (3DICs) and 2.5D chiplet-based architectures has introduced substantial complexity into physical signoff verification (PV) flows. These advanced designs feature heterogeneous die stacking, multi-node integration, Through-Silicon Vias (TSVs), micro-bumps, and silicon interposers—each posing unique verification challenges that exceed the capabilities of conventional EDA tools. Additionally, Electrostatic Discharge (ESD) signoff across stacked dies and inter-die interfaces requires novel modeling techniques and rule-checking strategies to ensure reliability. This paper presents Marvell's advanced PV methodology, which incorporates scalable rule-based and pattern-matching verification engines, automated topology extraction, and shift-left debugging strategies. The proposed framework enables early detection of physical and electrical violations across complex 3DIC topologies, supports multi-die and multi-foundry environments, and ensures comprehensive signoff coverage. Experimental results demonstrate significant improvements in verification throughput and a reduction in late-stage design iterations, validating the framework's effectiveness for next-generation heterogeneous systems.
Event Type
Engineering Presentation
TimeMonday, July 2710:45am - 11:00am PDT
LocationSeaside RM 7