Presentation
Modeling and Optimization of Power MOSFET Device Layouts with Optislang Tool
DescriptionThe performance of large semiconductor devices, such as power MOSFETS that carry large currents, depends not only on their size or area but also their layout and package implementation choices. Factors such as device aspect ratios, metal routing strategies and pad locations influence current flow through the device and impact device characteristics such as its on resistance (Rdson) and reliability.
It has been challenging to model these layout and configuration dependent effects. Optimizing the device layouts and pad configurations has been a manually iterative and time-consuming task, often done towards the end of the design cycle, resulting in increased risk of sub-optimal designs.
We propose a new methodology utilizing the features available in Ansys (now Synopsys) optiSLang tool to address this problem. We demonstrate a novel flow which integrates Cadence Virtuoso p-cell/skill scripts for device layout generation with Ansys Totem tool with PMIC utility for layout extraction and analysis. We utilize in-built optiSLang algorithms to run sensitivity analysis and develop meta-models. We envision a flow where process technology or PDK development teams will generate a device meta-model early on which can be exported as a python function. Design or packaging teams can use the simple function to identify and implement optimally sized devices as per their product requirements.
We will present a couple of examples to describe the optiSLang based flows and present power MOSFET device modeling and optimization results.
It has been challenging to model these layout and configuration dependent effects. Optimizing the device layouts and pad configurations has been a manually iterative and time-consuming task, often done towards the end of the design cycle, resulting in increased risk of sub-optimal designs.
We propose a new methodology utilizing the features available in Ansys (now Synopsys) optiSLang tool to address this problem. We demonstrate a novel flow which integrates Cadence Virtuoso p-cell/skill scripts for device layout generation with Ansys Totem tool with PMIC utility for layout extraction and analysis. We utilize in-built optiSLang algorithms to run sensitivity analysis and develop meta-models. We envision a flow where process technology or PDK development teams will generate a device meta-model early on which can be exported as a python function. Design or packaging teams can use the simple function to identify and implement optimally sized devices as per their product requirements.
We will present a couple of examples to describe the optiSLang based flows and present power MOSFET device modeling and optimization results.
Event Type
Engineering Presentation
TimeTuesday, July 282:30pm - 2:45pm PDT
LocationSeaside RM 7