Presentation
BIMEM-RAG: Reinforced Dual Memory Retrieval with Bidirectional Reasoning for RTL Synthesis and Summarization
DescriptionAutomating Register-Transfer Level (RTL) code generation and summarization is critical for improving hardware design productivity and reducing time-to-market. However, existing approaches struggle due to limited Verilog and VHDL training data and the structural concurrency inherent in hardware description languages (HDLs). We propose BiMem-RAG, a dual-memory retrieval and bidirectional reasoning framework for HDL synthesis and documentation. BiMem-RAG combines (i) an exemplar memory of specification-to-code and code-to-summary pairs indexed using joint code and abstract syntax tree embeddings, and (ii) an analogical memory capturing reusable hardware design patterns such as sequential and combinational logic. The system employs modular decomposition, reinforcement-guided retrieval, and backward verification to improve semantic fidelity and reduce hallucinations. Experiments on Verilog and VHDL benchmarks demonstrate up to 19 percentage-point improvements in Pass@1 and 9-point gains in ROUGE-L over strong baselines. These results show that structured retrieval and verification significantly improve RTL generation and summarization, enabling more reliable hardware design automation.
Event Type
Engineering Presentation
TimeTuesday, July 2811:00am - 11:15am PDT
LocationSeaside Ballroom A