Presentation
Attacking AES-XTS in Simulation: Pre-Silicon Side-Channel Leakage Assessment
DescriptionThis work presents a pre-silicon side-channel leakage assessment of an open-source AES-XTS hardware implementation at the RTL level. The complete encryption flow is functionally verified, and switching activity is captured and converted into high-resolution waveform data for power reconstruction. A Test Vector Leakage Assessment (TVLA) and Correlation Power Analysis (CPA) are applied to identify statistically significant leakage across encryption cycles and the key byte disclosures. Results reveal dominant leakage during early intermediate datapath operations, motivating targeted security refinement. The study demonstrates the effectiveness of integrating vector-based power reconstruction with systematic leakage evaluation to expose vulnerabilities prior to fabrication, enabling cost-effective mitigation and improved hardware security robustness.
Event Type
Engineering Presentation
TimeWednesday, July 2911:00am - 11:15am PDT
LocationSeaside Ballroom B