Presentation
A Soft-Microcode Engine to Power the Next Wave of Edge Intelligence
SessionSystem & Software Deployment
DescriptionThis paper presents a CISC processor architecture designed for modern CMOS technology, featuring a compact and flexible datapath capable of operating efficiently on arbitrary data formats. The architecture supports high-level languages as well as graphics, signal processing, memory, and I/O workloads within a unified execution model.
The processor has evolved over several decades, from a TTL-based minicomputer to multiple generations of CMOS microprocessors implemented in different fabrication nodes. It has been deployed in a wide range of commercial applications worldwide. A recent dual-core implementation has been silicon-verified in 65 nm technology, and a corresponding 22 nm design has been functionally validated on FPGA.
Measured results demonstrate high energy efficiency, strong code density, and extensive support for specialized processing and peripheral control. Because much of the system functionality is implemented in writable microcode rather than fixed hardware, the architecture is well suited as a control processor in universal SoCs targeting mid-volume IoT/OT devices, where custom SoC development is impractical.
The core can also function as a processing element in AI accelerators, with microcode distributed across clustered PEs to implement individual DNN layers.
The processor has evolved over several decades, from a TTL-based minicomputer to multiple generations of CMOS microprocessors implemented in different fabrication nodes. It has been deployed in a wide range of commercial applications worldwide. A recent dual-core implementation has been silicon-verified in 65 nm technology, and a corresponding 22 nm design has been functionally validated on FPGA.
Measured results demonstrate high energy efficiency, strong code density, and extensive support for specialized processing and peripheral control. Because much of the system functionality is implemented in writable microcode rather than fixed hardware, the architecture is well suited as a control processor in universal SoCs targeting mid-volume IoT/OT devices, where custom SoC development is impractical.
The core can also function as a processing element in AI accelerators, with microcode distributed across clustered PEs to implement individual DNN layers.
Event Type
Engineering Presentation
TimeMonday, July 273:30pm - 3:45pm PDT
LocationSeaside Ballroom B
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