Presentation
Enabling Early Thermal Insight in Heterogeneous Integration Through Implementation-Driven Power Modeling
DescriptionAs semiconductor designs scale toward higher power densities and heterogeneous integration, the prediction of thermal behavior at early design stage becomes essential for both performance and reliability. Conventional board-level thermal models use simplified uniform power assumptions which fail to capture localized hotspots. Whereas high resolution power maps generated require high design collaterals, which are available only at sign-off, and are computationally expensive.
We overcome these limitations by creating a high-resolution, tile-based power map using the instance power and location files from the implementation tools and on-die routing information from GDSII file of a former design. This generates the detailed power map nearly 2x faster, with less than 2% loss in accuracy compared to the currently available methods of generation using EM-IR sign-off tools.
We demonstrated this method on a 2DIC design with the power map consisting of multiple blocks of different functionalities stitched together. The package model and heat sink system is included. The junction temperatures obtained using this method yielded 4-5°C more accurate temperatures against simplified block power based thermal analysis. This methodology helps in analyzing the thermal behavior of the chip at very early design stages and designing appropriate system level cooling solutions.
We overcome these limitations by creating a high-resolution, tile-based power map using the instance power and location files from the implementation tools and on-die routing information from GDSII file of a former design. This generates the detailed power map nearly 2x faster, with less than 2% loss in accuracy compared to the currently available methods of generation using EM-IR sign-off tools.
We demonstrated this method on a 2DIC design with the power map consisting of multiple blocks of different functionalities stitched together. The package model and heat sink system is included. The junction temperatures obtained using this method yielded 4-5°C more accurate temperatures against simplified block power based thermal analysis. This methodology helps in analyzing the thermal behavior of the chip at very early design stages and designing appropriate system level cooling solutions.
Event Type
Engineering Presentation
TimeMonday, July 274:30pm - 4:45pm PDT
LocationSeaside Ballroom A