Presentation
Past Present and Future of CDC & RDC Glitches: Improved Glitch Checker (IGC)
DescriptionCDC & RDC verification faces critical challenges where synthesis optimization introduces glitches undetectable during RTL analysis but manifest as silicon failures, significantly impacting Time to Market. Improved Glitch Checker is a novel three-stage methodology addressing synthesis-induced CDC and RDC issues that traditional EDA tools fail to capture.
The core problem arises when synthesis tools perform Boolean algebraic optimizations that maintain logical equivalence but introduce timing hazards. For example, the expression A & EN may be optimized to A & (~A + EN) using distributive laws, which algebraically simplifies (A & ~A) + (A & EN) = A & EN. While functionally equivalent, this optimization creates a critical timing vulnerability: when signal A transitions while EN=0, both A and ~A change simultaneously in opposite directions, causing the intermediate AND gate (A & ~A) to momentarily glitch before settling to zero. This glitch can propagate through the CDC and RDC path, violating metastability requirements and causing silicon failures that are impossible to detect during RTL-level CDC and RDC analysis.
Our three-stage solution employs: (1) Netlist Cone Extraction for targeted combinational logic, (2) Formal glitch analysis using Z3 satisfiability solving, and (3) Don't-Touch cell integration preventing synthesis optimization of critical CDC paths. Enablement of the solution demonstrates successful prevention of synthesis-induced CDC & RDC violations, reducing months of silicon debug time.
The core problem arises when synthesis tools perform Boolean algebraic optimizations that maintain logical equivalence but introduce timing hazards. For example, the expression A & EN may be optimized to A & (~A + EN) using distributive laws, which algebraically simplifies (A & ~A) + (A & EN) = A & EN. While functionally equivalent, this optimization creates a critical timing vulnerability: when signal A transitions while EN=0, both A and ~A change simultaneously in opposite directions, causing the intermediate AND gate (A & ~A) to momentarily glitch before settling to zero. This glitch can propagate through the CDC and RDC path, violating metastability requirements and causing silicon failures that are impossible to detect during RTL-level CDC and RDC analysis.
Our three-stage solution employs: (1) Netlist Cone Extraction for targeted combinational logic, (2) Formal glitch analysis using Z3 satisfiability solving, and (3) Don't-Touch cell integration preventing synthesis optimization of critical CDC paths. Enablement of the solution demonstrates successful prevention of synthesis-induced CDC & RDC violations, reducing months of silicon debug time.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor