Presentation
Structure Aware Clock Tree Synthesis Using Width-Driven CTS Cell Constraints
DescriptionModern Clock Tree Synthesis (CTS) relies on heterogeneous clock cells with wide variations in physical width, drive strength, and area. However, existing CTS placement controls such as density-based halos apply uniform or linearly scaled spacing that is largely agnostic to clock tree structure and stage-specific requirements. This often leads to suboptimal clock cell clustering, irregular latency gradients, increased power, and degraded clock skew consistency across corners.
This paper presents a structure-aware CTS methodology that leverages cell-width–based classification to guide clock cell placement using explicit CTS halo attributes. By mapping physical base-cell widths of buffers and inverters to non-uniform X-direction clock halos, the proposed approach implicitly encodes top, trunk, and leaf placement intent during CTS construction.
The proposed method is implemented entirely using tool-native CTS attributes and requires no modification to the CTS engine. Experimental results on a production-scale design demonstrate reductions in clock cell count, clock area, wirelength, and congestion, along with improved latency smoothness and multi-corner clock skew consistency, with negligible impact on target skew. This work shows that physical-aware halo modulation provides an effective and scalable mechanism for robust clock tree optimization.
This paper presents a structure-aware CTS methodology that leverages cell-width–based classification to guide clock cell placement using explicit CTS halo attributes. By mapping physical base-cell widths of buffers and inverters to non-uniform X-direction clock halos, the proposed approach implicitly encodes top, trunk, and leaf placement intent during CTS construction.
The proposed method is implemented entirely using tool-native CTS attributes and requires no modification to the CTS engine. Experimental results on a production-scale design demonstrate reductions in clock cell count, clock area, wirelength, and congestion, along with improved latency smoothness and multi-corner clock skew consistency, with negligible impact on target skew. This work shows that physical-aware halo modulation provides an effective and scalable mechanism for robust clock tree optimization.
Event Type
Engineering Presentation
TimeWednesday, July 292:45pm - 3:00pm PDT
LocationSeaside RM 7