Presentation
ANA-MODELGEN: Automating Analog IP Model Generation and Validation for Efficient Mixed-Signal Verification
DescriptionAnalog IP verification remains a bottleneck in modern mixed-signal SoC development due to lengthy SPICE simulation times and integration challenges. This paper introduces ANA-MODELGEN, a comprehensive hierarchical modeling methodology that transforms analog IP verification through automated model generation and validation. Our approach enables rapid development and validation of behavioral models for any analog IP type, featuring direct integration capabilities with industry-standard verification environments. The methodology includes automated testbench generation for rigorous model validation and equivalence checking against SPICE references. Deployment in production SoC verification flows demonstrates substantial gains in functional coverage and execution speed, enabling earlier bug detection and faster time-to-market.
Event Type
Engineering Presentation
TimeTuesday, July 2811:00am - 11:15am PDT
LocationSeaside Ballroom B