Presentation
From Design to Defense: Pioneering Pre-Silicon Leakage Detection for Novel ECC Crypto Core
DescriptionWe present a practical pre-silicon methodology for identifying power side-channel leakage in elliptic-curve cryptography (ECC) hardware before tape-out. The approach leverages sign-off–quality activity and power artifacts to expose data-dependent leakage early in the design flow. Cryptography-aware stimuli are applied to ECC RTL to generate switching activity, followed by time-resolved dynamic power estimation and automated Welch's t-test (TVLA) analysis. The target design is an Elliptic Curve Diffie–Hellman (ECDH) core, an ECC-based IP that relies on scalar multiplication, implemented with a Karatsuba-based field multiplier optimized for area–delay efficiency. Initial analysis of the unprotected implementation reveals clear and repeatable leakage during the first cycle of the design, corresponding to public key computation. Although ECC is mathematically robust, complex arithmetic and data-dependent behavior can unintentionally reveal sensitive information through physical side channels if not addressed during implementation. Our goal is to surface such risks using analysis flows already trusted for power, performance, and area validation.
Beyond pass/fail screening, the methodology localizes dominant leakage contributors in time and logic, enabling targeted mitigation. The flow is fully scriptable, reuses standard sign-off tools, and integrates naturally into implementation regressions. Although demonstrated on ECC, the method generalizes to other cryptographic accelerators and security-critical hardware, providing a scalable path to pre-silicon side-channel hardening.
Beyond pass/fail screening, the methodology localizes dominant leakage contributors in time and logic, enabling targeted mitigation. The flow is fully scriptable, reuses standard sign-off tools, and integrates naturally into implementation regressions. Although demonstrated on ECC, the method generalizes to other cryptographic accelerators and security-critical hardware, providing a scalable path to pre-silicon side-channel hardening.
Event Type
Engineering Presentation
TimeWednesday, July 2911:15am - 11:30am PDT
LocationSeaside Ballroom B