Presentation
UVM-MS: A Novel Approach to Mixed-Signal IP Verification
DescriptionTraditional analog mixed-signal (MS) IP verification relies heavily on analog-centric simulations, such as Monte Carlo simulations, which focus solely on analog behavior . This approach leads to significant drawbacks, including the inability to accurately model loading effects, kickbacks, and reference/supply variations, resulting in potential silicon bugs. Furthermore, the use of Verilog-AMS models and connect modules introduces additional complexities, leading to prolonged simulation runtimes and limited functional coverage. To address these challenges, this paper proposes a novel UVM-MS based verification methodology that leverages VIPs (Verification Intellectual Property) to drive and monitor analog signals, providing comprehensive coverage of digital-analog interactions. Our approach eliminates the need for connect modules, reduces simulation runtime, and enhances functional coverage, thereby improving the overall verification efficiency of MS IPs. By adopting this new methodology, designers can ensure more accurate and reliable verification of their MS IPs, reducing the risk of silicon bugs and improving time-to-market.
Event Type
Engineering Presentation
TimeMonday, July 2710:45am - 11:00am PDT
LocationSeaside Ballroom A
Similar Presentations