Presentation
Scalable Hierarchical EMIR Analysis Using Multi Layered Abstraction for Reticle-Scale Data Centre SOCs
DescriptionReticle-scale SoCs and repetitive compute fabrics have fundamentally altered the scalability requirements of EMIR signoff. Modern designs composed of large, clustered subsystems and shared routing channels expose critical limitations in conventional flat EMIR analysis flows, including multi-day runtimes, compute memory saturation, and unmanageable activity data volumes. EDA Tool based boundary abstraction partially restores current accuracy but ignores logic interaction and propagation, limiting its effectiveness for localized IR detection. LEF with current profile abstraction of blocks improves scalability but smoothens current distribution, underestimating boundary bump currents and masking rail-sharing and temporal switching correlations.
This work presents a novel hierarchical and interaction-aware hybrid EMIR analysis methodology that combines region-based clustering with an abstraction strategy that selectively applies Reduced-Order EDA Models and LEF with current profile abstraction based on electrical sensitivity and interaction criticality. This mixed modeling approach enables accurate logic propagation, realistic switching correlation, and precise modeling of rail sharing and bump contention without incurring the cost of full flat simulation.
The proposed flow achieves up to 10× runtime reduction, 50% reduction in memory and database footprint and extremely good correlation with flat EM/IR signoff. The methodology is production-proven, easily adoptable within existing signoff flows, and directly applicable to next-generation reticle-scale, AI/ML SoC architectures.
This work presents a novel hierarchical and interaction-aware hybrid EMIR analysis methodology that combines region-based clustering with an abstraction strategy that selectively applies Reduced-Order EDA Models and LEF with current profile abstraction based on electrical sensitivity and interaction criticality. This mixed modeling approach enables accurate logic propagation, realistic switching correlation, and precise modeling of rail sharing and bump contention without incurring the cost of full flat simulation.
The proposed flow achieves up to 10× runtime reduction, 50% reduction in memory and database footprint and extremely good correlation with flat EM/IR signoff. The methodology is production-proven, easily adoptable within existing signoff flows, and directly applicable to next-generation reticle-scale, AI/ML SoC architectures.
Event Type
Engineering Presentation
TimeMonday, July 273:30pm - 3:45pm PDT
LocationSeaside Ballroom A