Presentation
A Programmable, Synthesizable CMOS Analog Optimization IP Core for Real-Time Control
DescriptionThis work presents an automated EDA toolchain for synthesizing programmable and scalable CMOS analog optimization IP cores. Addressing the latency wall in real-time control, where conventional digital solvers face polynomial scaling bottlenecks, our methodology translates high-level mathematical specifications (AMPL/MPS) directly into verification-ready SPICE netlists. The synthesized IP utilizes a reconfigurable switched-capacitor architecture that implements continuous-time Karush-Kuhn-Tucker dynamics, allowing it to solve constrained optimization problems through parallel physics-based evolution rather than sequential algorithms.Unlike prior art limited to small-scale fixed-function circuits, our architecture incorporates a software-driven calibration layer to neutralize PVT variations, ensuring reliability in standard CMOS nodes. We demonstrate the flow's scalability on problem sizes ranging from dense 500-variable instances to sparse 10,000-variable workloads. Results show the generated IP achieves invariant sub-millisecond convergence regardless of complexity, delivering a >300X speedup over state-of-the-art digital interior-point solvers while maintaining solution accuracy within 0.02% relative error. This work provides a complete code-to-silicon path for deploying high-performance analog computing in edge AI and real-time control systems.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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