Presentation
Lint-Free: A Generative AI Approach to Large Scale Autonomous RTL-Lint Correction
DescriptionThe increasing complexity and scale of modern ASIC designs have made RTL linting a critical yet challenging aspect of the hardware development process. Traditional manual linting workflows are slow, error-prone, and often overwhelmed by the sheer volume of warnings and errors generated by industry-standard tools. This bottleneck not only delays design cycles but also forces teams into undesirable tradeoffs between speed and code quality.
In this work, we present a novel, fully automated RTL lint remediation platform that leverages codemod technology—previously successful in software engineering—and adapts it for hardware design. Our system proactively scans RTL codebases using nightly runs of industry-standard lint tools, applies context-aware automated fixes, and validates each change through rigorous RTL lint and design verification (DV) workflows. Disruptive or faulty changes are automatically triaged, while human-in-the-loop review ensures correctness and maintains expert oversight.
By automating repetitive error correction and integrating robust validation, our solution enables ASIC engineers to focus on high-value design tasks, significantly improving both efficiency and code quality.
This work represents a step-change in RTL design automation, bridging the gap between software and hardware codemod practices, and offers a scalable, adaptive, and reliable framework for next-generation ASIC development.
In this work, we present a novel, fully automated RTL lint remediation platform that leverages codemod technology—previously successful in software engineering—and adapts it for hardware design. Our system proactively scans RTL codebases using nightly runs of industry-standard lint tools, applies context-aware automated fixes, and validates each change through rigorous RTL lint and design verification (DV) workflows. Disruptive or faulty changes are automatically triaged, while human-in-the-loop review ensures correctness and maintains expert oversight.
By automating repetitive error correction and integrating robust validation, our solution enables ASIC engineers to focus on high-value design tasks, significantly improving both efficiency and code quality.
This work represents a step-change in RTL design automation, bridging the gap between software and hardware codemod practices, and offers a scalable, adaptive, and reliable framework for next-generation ASIC development.
Event Type
Engineering Presentation
TimeWednesday, July 2911:45am - 12:00pm PDT
LocationSeaside Ballroom A