Presentation
Optimizing Digital SOC Designs, One Cell at a Time Using AI Transistor-Level Sizing
DescriptionStandard cell libraries form the foundation of SoC design but impose significant limitations through fixed drive strengths, P/N ratios, and tapering schemes. While typical libraries offer approximately 30 variants per gate type, the theoretical design space contains millions potential variants per gate. Traditional EDA tools cannot effectively explore this vast space, leaving substantial performance gains untapped.
This work introduces a novel methodology that optimizes power and performance through intelligent, selective transistor resizing at the individual cell level. The approach creates tailor-made cell variants while maintaining full compatibility with standard EDA flows. The method employs a two-stage process: a one-time per-Library precomputation phase that generates predictive models from SPICE models and library data, using AI techniques, followed by a per-design optimization flow that produces custom cell netlists.
This smart exploration of the design space identifies high-impact optimization opportunities without overwhelming existing tool flows. By enabling transistor-level customization within the standard cell framework, this methodology unlocks previously inaccessible performance improvements. Results on real industrial designs demonstrate double-digit percentage improvements in power efficiency and timing while seamlessly integrating into conventional design methodologies.
This work introduces a novel methodology that optimizes power and performance through intelligent, selective transistor resizing at the individual cell level. The approach creates tailor-made cell variants while maintaining full compatibility with standard EDA flows. The method employs a two-stage process: a one-time per-Library precomputation phase that generates predictive models from SPICE models and library data, using AI techniques, followed by a per-design optimization flow that produces custom cell netlists.
This smart exploration of the design space identifies high-impact optimization opportunities without overwhelming existing tool flows. By enabling transistor-level customization within the standard cell framework, this methodology unlocks previously inaccessible performance improvements. Results on real industrial designs demonstrate double-digit percentage improvements in power efficiency and timing while seamlessly integrating into conventional design methodologies.
Event Type
Engineering Presentation
TimeMonday, July 271:30pm - 1:45pm PDT
LocationSeaside Ballroom B
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