Presentation
Scalable Verification Methodology for Stacked 3D Chiplet-Based Designs Using SIP Flow
SessionSystem & Software Design
DescriptionMarvell's latest designs are 3D chiplet-based architectures, where multiple dies are stacked into a single package. Our 3D platform is a dual-die project featuring advanced die-to-die (D2D) interconnect technology, with a top die and bottom die built on 3nm and 5nm process nodes. Verifying such systems is challenging because traditional design verification flows are built for single chips. Issues include common module names (like PLL) that differ across dies, and directory structures that don't easily support multi-die integration. To address these challenges, we introduced the System in Package (SIP) flow using sipreg, a tool that builds and executes one or more SIP simulations. Unlike legacy flows, SIP enables users to incorporate chiplet design components into a single monolithic simulation executable by leveraging the VCS 3-step flow - analysis, elaboration, and simulation - along with logical Verilog libraries. Logical libraries allow design components to be analyzed into named libraries (vlibs) and reused during elaboration, giving SIP project leads flexibility to select chiplet components as building blocks for system-level simulations. These solutions, now deployed on our multi-die test chip, enable scalable verification for chiplet-based designs and streamline future multi-die projects.
Event Type
Engineering Presentation
TimeMonday, July 2711:06am - 11:24am PDT
LocationSeaside Ballroom B